Importance

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Abstract

A memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.

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First Claim