SYNCHRONISED MULTI-PROCESSOR OPERATING SYSTEM TIMER
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 26, 2024
app pub date -
Jul 11, 2022
filing date -
Jul 13, 2021
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
An integrated-circuit device comprises a plurality of processor cores and a system timer. The system timer includes a first oscillator that outputs a first clock signal at a first frequency, a first counter register incremented by the first clock signal and a plurality of event registers. Each event register triggers an event when a value held therein is determined to be equal to a value held in the first counter register. The first counter register is readable by each of the plurality of processor cores, and each of the processor cores are capable of writing to at least one of the event registers.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully