Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector
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United States of America Patent
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Oct 15, 2024
Grant Date -
Sep 19, 2024
app pub date -
Mar 13, 2023
filing date -
Mar 13, 2023
priority date (Note) -
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Abstract
This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.
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