SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
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United States of America Patent
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Issued Date -
Sep 19, 2024
app pub date -
Aug 5, 2021
filing date -
Aug 5, 2021
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Abstract
A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.
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