MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ
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United States of America Patent
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Issued Date -
Sep 19, 2024
app pub date -
May 28, 2024
filing date -
May 28, 2020
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Abstract
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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