SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS

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United States of America Patent

APP PUB NO 20240304543A1
SERIAL NO

18668038

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bielefeld, Jeffery Forest Grove, US 12 22
Blackwell, James M Portland, US 54 622
Chandhok, Manish Beaverton, US 109 527
Chebiam, Ramanan Hillsboro, US 13 462
Chen, Jiun-Ruey Hillsboro, US 9 11
Christenson, Michael Beaverton, US 9 157
Jezewski, Christopher Portland, US 29 147
Kabir, Nafees Hillsboro, US 16 39
Karpov, Elijah Portland, US 20 180
Lin, Kevin Beaverton, US 166 1997
Metz, Matthew Portland, US 92 887
Naylor, Carl Portland, US 32 66
Reshotko, Miriam Portland, US 22 85
Sato, Noriyuki Hillsboro, US 188 791
Tronic, Tristan Aloha, US 18 20
Yoo, Hui Jae Hillsboro, US 100 509

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