Masking Techniques for Memory Applications
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United States of America Patent
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Issued Date -
Sep 12, 2024
app pub date -
Jul 7, 2023
filing date -
Mar 8, 2023
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Abstract
Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.
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