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Abstract

An analog-to-digital conversion circuit is provided. The analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) and a debounce controller. The ADC is configured to sequentially convert an analog input signal into a plurality of conversion bits in response to a plurality of cycles of a clock signal. The debounce controller is configured to sequentially receive the conversion bits in response to each of the cycles of the clock signal. In each of the cycles, the debounce controller is configured to integrate the received conversion bits into conversion data and to determine whether the conversion data exceeds a normal range. When the conversion data exceeds the normal range, the debounce controller is configured to provide an abort signal to the analog-to-digital converter, so that the analog-to-digital converter stops converting the analog input signal.

First Claim