LOW-POWER FLIP FLOP CIRCUIT
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United States of America Patent
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Issued Date -
Sep 5, 2024
app pub date -
Apr 25, 2024
filing date -
Nov 30, 2016
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Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
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