MEMORY DEVICE WITH DUAL INTERFACE, TEST METHOD AND TEST SYSTEM THEREOF
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United States of America Patent
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Issued Date -
Sep 5, 2024
app pub date -
Nov 16, 2023
filing date -
Mar 1, 2023
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Abstract
Disclosed is a memory device with dual interface, test method and test system thereof. An initialization procedure is executed by the memory device with dual interface in a PCIe mode. A voltage level of a pin of the memory device with dual interface is altered according to the initialization procedure, wherein the pin of the memory device with dual interface operates in a SD mode but not in PCIe mode. The voltage level of the pin of the memory device with dual interface is switched between a high voltage level and a low voltage level at a first frequency during a test stage of the initialization procedure. The voltage level of the pin of the memory device with dual interface is kept at the high voltage level or the low voltage level during a result display stage of the initialization procedure.
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