NON-VOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLS
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United States of America Patent
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Issued Date -
Sep 5, 2024
app pub date -
May 13, 2024
filing date -
Dec 31, 2019
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Abstract
Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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