MEMORY SYSTEMS AND DEVICES THAT SUPPORT METHODS FOR CALIBRATING INPUT OFFSETS THEREIN
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United States of America Patent
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Issued Date -
Sep 5, 2024
app pub date -
Sep 12, 2023
filing date -
Mar 3, 2023
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Abstract
A memory device includes a memory cell array and an input/output circuit. The input/output circuit is configured to: (i) generate second data in response to sampling first data by comparing the first data against a reference voltage, (ii) generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code, (iii) change a gain of an input buffer corresponding to the mode register code after receiving the mode register code, and (iv) calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code. Control logic may also be used to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.
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