PHASE LOCKED LOOP CIRCUIT
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Aug 29, 2024
app pub date -
Feb 19, 2024
filing date -
Feb 28, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A deadlock detection circuit 20 determines that deadlock occurs, sets a switching signal 106 to H level when a control voltage 104 exceeds an upper limit set in advance, and set the switching signal to L level when the control voltage 104 is lower than a lower limit set in advance. When the switching signal 106 reaches H level, multiplexers 12, 13 perform switching, so that, in place of a reference clock signal 101, an L level signal is input to a phase frequency detector 14, and, in place of a feedback clock signal 107, the reference clock signal 101 is input to the phase frequency detector 14.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully