Importance

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Abstract

Methods, systems, and devices for split pillar and pier memory architectures are described. A memory array may include a first set of word line plates separated from a second set of word line plates by a trench and a set of pairs of pillars (e.g., that are configured as digit lines) that interact with the first and second set of word line plates. Further, the memory array may include a set of dielectric piers that are positioned between the pairs of pillars, where each dielectric pier contacts a first pillar from a first pair and a second pillar from a second pair. Additionally, the memory array may include a set of storage elements that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.

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First Claim