INTEGRATED CIRCUIT (IC) PACKAGE INCLUDING A CAPACITOR FORMED IN A CONDUCTIVE ROUTING REGION
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United States of America Patent
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Issued Date -
Aug 22, 2024
app pub date -
Jun 28, 2023
filing date -
Feb 21, 2023
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Abstract
An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region formed over the bare die, the conductive routing region including a conductive routing structure and a capacitor formed in multiple conductive routing layers. The bare die includes IC circuitry, a dielectric region at least partially encapsulating the IC circuitry, and an IC contact exposed through the dielectric region. The conductive routing structure formed in the conductive routing region is conductively connected to the IC contact of the bare die. The capacitor formed in the conductive routing region includes a first capacitor electrode and a second capacitor electrode formed in one or more of the conductive routing layers, and a capacitor dielectric element formed between the first capacitor electrode and the second capacitor electrode.
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