ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION

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United States of America Patent

APP PUB NO 20240282632A1
SERIAL NO

18109365

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Abstract

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A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhuyan, Bhaskar Jyoti Santa Clara, US 98 526
Devereaux, Zachary J Webberville, US 2 0
Knisley, Thomas Joseph Livonia, US 26 1609
Mallick, Abhijit Basu Fremont, US 266 12114
Roy, Susmit Singha Campbell, US 46 264
Saly, Mark J Santa Clara, US 20 568
Shen, Zeqing San Jose, US 30 2

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