OUTPUT BLOCK FOR ARRAY OF NON-VOLATILE MEMORY CELLS

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United States of America Patent

APP PUB NO 20240282351A1
SERIAL NO

18195322

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Abstract

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In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.

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Patent Owner(s)

Patent OwnerAddress
SILICON STORAGE TECHNOLOGY INC450 HOLGER WAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
HONG, STANLEY San Jose, US 98 237
LE, NGHIA Ho Chi Minh, VN 7 5
NGUYEN, DUC Ho Chi Minh, VN 23 186
PHAM, HIEN Ho Chi Minh, VN 26 74
TRAN, HIEU VAN San Jose, US 354 3483
TRINH, STEPHEN San Jose, US 62 144
VU, HOA Milpitas, US 23 149
VU, THUAN San Jose, US 117 299

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