SEMICONDUCTOR MEMORY DEVICE
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Aug 15, 2024
app pub date -
Feb 13, 2024
filing date -
Feb 14, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
According to one embodiment, a semiconductor memory device includes a plurality of conductor layers including a first conductor layer as an uppermost layer; a plurality of memory pillars penetrating the conductor layers; and a member that includes a first portion extending in the conductor layers and a plurality of second portions RT provided apart from each other on the uppermost layer side of the conductor layers, and divides the conductor layers in a direction in a substrate surface; wherein a lower surface of the second portion is located below an upper surface of the first conductor layer, and an upper surface of the second portion is wider in a width in the direction, than the lower surface of the second portion and than the first portion.
First Claim
Family
International Classification(s)
- No Non-US Classification to display
Cited Art Landscape
Patent Citation Ranking
- Citation Ranking not provided
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully