Importance

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Abstract

Provided is a DRAM including includes bit line stack patterns on a substrate, spacers on sidewalls of the bit line stack patterns, capacitor contacts electrically connected to active regions in the substrate, and capacitor landing pads covering the capacitor contacts, first portions of the spacers, and a portion of the bit line stack patterns. In each spacer, a second dielectric layer is located between a lower portion of a first dielectric layer and a lower portion of a third dielectric layer, and a fourth dielectric layer is located between an upper portion of the first dielectric layer and an upper portion of the third dielectric layer. Top surfaces of second portions of the plurality of spacers not covered by the plurality of capacitor landing pads are lower than top surfaces of the first portions of the plurality of spacers.

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First Claim