PCB STACK WITH EMBEDDED COMPONENT PACKAGE AND SINTERED VIAS
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United States of America Patent
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Issued Date -
Aug 15, 2024
app pub date -
Jul 7, 2023
filing date -
Feb 9, 2023
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Abstract
A method by attaching a component to a first PCB, positioning a prepreg, having a via hole and a component cavity, proximate the first PCB with the component in the component cavity, putting a conductive material in the via hole of the prepreg, positioning a second PCB proximate the first PCB with the component and prepreg between the first PCB and the second PCB, and curing the conductive material to form a sintered via connecting the first PCB with the second PCB. A device with a first PCB, a component attached to the first PCB, a second PCB proximate the first PCB with the component between the first PCB and the second PCB, and a sintered metal via of conductive material connecting the first PCB with the second PCB.
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