NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
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United States of America Patent
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Issued Date -
Aug 15, 2024
app pub date -
Oct 31, 2023
filing date -
Feb 14, 2023
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Abstract
Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.
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