PAGE BUFFER PERFORMING MEMORY OPERATION
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United States of America Patent
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Issued Date -
Aug 15, 2024
app pub date -
Aug 8, 2023
filing date -
Feb 9, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
The present technology relates to an electronic device. According to the present technology, a page buffer may include a bit line voltage control circuit, a latch and a reference voltage supply circuit. The bit line voltage control circuit may selectively connect a bit line and a sensing node. The latch may provide a latch signal corresponding to data. The reference voltage supply circuit may include a first PMOS transistor and a first NMOS transistor coupled in series between the sensing node and a ground voltage terminal, and apply a first reference voltage to the sensing node. The first PMOS transistor may be controlled according to the reference voltage control signal. The first NMOS transistor may be controlled by the latch signal.
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