PHASE LOCK LOOP REFERENCE LOSS DETECTION
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United States of America Patent
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Issued Date -
Aug 8, 2024
app pub date -
Apr 17, 2024
filing date -
Oct 22, 2018
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Abstract
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
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