NANO-FET SEMICONDUCTOR DEVICE AND METHOD OF FORMING
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United States of America Patent
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Aug 8, 2024
app pub date -
Mar 27, 2024
filing date -
Mar 26, 2021
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Abstract
Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.
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