POWER OVERLAY PACKAGE FOR A SEMICONDUCTOR DEVICE
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United States of America Patent
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Issued Date -
Aug 8, 2024
app pub date -
Feb 8, 2023
filing date -
Feb 8, 2023
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Abstract
A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.
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