NON-VOLATILE MEMORY CELL STRUCTURES AND METHODS OF MANUFACTURING THEREOF
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United States of America Patent
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Issued Date -
Aug 1, 2024
app pub date -
Jan 30, 2023
filing date -
Jan 30, 2023
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Abstract
A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.
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