Importance

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Abstract

The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.

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First Claim