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Abstract

A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.

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First Claim