METHOD AND SYSTEM FOR ETCH DEPTH CONTROL IN III-V SEMICONDUCTOR DEVICES
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United States of America Patent
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Issued Date -
Jul 18, 2024
app pub date -
Mar 28, 2024
filing date -
Jun 26, 2020
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Abstract
A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.
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