PACKET SORTING AND REASSEMBLY CIRCUIT MODULE
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United States of America
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May 7, 2024
Grant Date -
Apr 25, 2024
app pub date -
Jan 16, 2023
filing date -
Jan 16, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.
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