MEMORY DEVICE AND METHOD
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United States of America Patent
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Issued Date -
Jul 11, 2024
app pub date -
Mar 25, 2024
filing date -
Nov 22, 2021
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Abstract
An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time to digital convertor converts a time associated with the output voltage to a digital value.
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