Method for Generating Placement and Routing for an Integrated Circuit (IC)
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 11, 2024
app pub date -
Jan 5, 2023
filing date -
Jan 5, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A technology is described for generating placement and routing for a netlist of an integrated circuit (IC) design. The netlist for the IC design is partitioned into multiple subsets of cells. The subsets of cells are prioritized. Multiple stepwise place and route iterations are performed for the multiple subsets of cells. A first subset of cells with a first priority is placed in an arrangement representing the IC design. Wire connections are routed between the cells of the first subset of cells. A second subset of cells is placed relative to one another and the first subset of cells in the arrangement. Wire connections are routed between the cells of the second subset of cells and the cells of the first subset of cells.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully