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Abstract

A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

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First Claim