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Abstract

Disclosed is a phase-locked loop device. The phase-locked loop device includes a frequency-locked loop circuit and a phase-locked loop circuit. The frequency-locked loop circuit includes a delay generator circuit and a frequency-phase detector. The delay generator circuit generates a ramp signal based on the feedback clock signal, and compares the ramp signal with multiple reference voltages to generate multiple delayed feedback clock signals. The frequency-phase detector has a dead zone control mechanism that generates a locking signal based on phases of the reference clock signal and delayed feedback clock signal and automatically switches on/off the dead zone. The phase-locked loop circuit generates the first output current according to the phase difference between the reference clock signal and the feedback clock signal.

First Claim