MULTI-PHASE CLOCK GATING WITH PHASE SELECTION
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United States of America Patent
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Issued Date -
Jul 4, 2024
app pub date -
Dec 31, 2022
filing date -
Dec 31, 2022
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Abstract
A multi-phase clock gating circuit receives a plurality of respective phased clock signals, and a one-hot stop phase select signal indicating a first selected phase for which gating of the phased clock signals is to be started. Responsive to a clock control signal indicating the phased clock signals are to be gated, the clock signals are gated beginning at the first selected phase, in order of phase, including looping from a last phase to a first phase.
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