WRONG WAY READ-BEFORE WRITE SOLUTIONS IN SRAM
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United States of America Patent
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Issued Date -
Jul 4, 2024
app pub date -
Dec 29, 2022
filing date -
Dec 29, 2022
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Abstract
A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.
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