AUTOMATED DESIGN-TO-LITHOGRAPHY AND DESIGN CHECKING FOR STITCHED INTEGRATED CIRCUIT DESIGN
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United States of America Patent
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Issued Date -
Jul 4, 2024
app pub date -
Dec 30, 2022
filing date -
Dec 30, 2022
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Abstract
An integrated circuit design is partitioned into a plurality of cells and a plurality of images of a stitched chip design are generated based on the plurality of cells. At least one of the images is wrapped with a chrome border and a blading outline to generate a mask design. Design information is extracted from the mask design and the stitched chip design. A scanner job file for fabricating the integrated circuit design is generated based on the extracted design information and the fabrication of an integrated circuit using the scanner job file is facilitated.
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