EMBEDDED DIE PACKAGING OF POWER SEMICONDUCTOR DEVICES

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United States of America Patent

APP PUB NO 20240213110A1
SERIAL NO

18085660

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Abstract

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Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

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Patent Owner(s)

Patent OwnerAddress
GAN SYSTEMS INC770 PALLADIUM DRIVE SUITE 201 OTTAWA K2V 1C8

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHENG, An-Sheng Hsinchu City, TW 3 0
COATES, Stephen San Francisco, US 13 73

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