Importance

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Abstract

Methods, systems, and devices for memory array circuit arrangement are described. A memory device may include a memory subarray, which may include a complementary metal oxide semiconductor (CMOS) circuitry under array (CuA) circuitry area and a word line driver region (e.g., word line driver circuitry) or a digit line driver region (e.g., digit line driver circuitry, sense amplifier circuitry multiplexed with the digit line driver circuitry). The memory subarray may include a first interconnect extending in a first and traversing at least a first portion of the CuA circuitry area of the memory subarray. The first interconnect may be coupled with the first portion of the CuA circuitry area and a first interconnection layer. Additionally, each memory subarray may include a second interconnect extending in a second direction and traversing at least a second portion of the CuA circuitry area of the memory subarray.

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First Claim