SPARSE MATRIX ACCELERATED COMPUTING METHOD AND APPARATUS, DEVICE, AND MEDIUM
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United States of America Patent
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Issued Date -
Jun 27, 2024
app pub date -
Nov 29, 2021
filing date -
Jan 8, 2021
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Abstract
A sparse matrix accelerated computing method and apparatus, a device, and a medium are disclosed. The method includes: reading and performing non-zero detection on a first sparse matrix, and generating first status information of each line of data of the first sparse matrix by the detection result and storing same into a register; storing non-zero data of the first sparse matrix into an RAM; reading and performing non-zero detection on a second sparse matrix, and generating second status information of each row of data of the second sparse matrix by a detection result and storing same into the register; and performing a logical operation on the first status information and the second status information, reading the data in the RAM by the logical operation result, and performing a product operation on the data in the RAM and data of the second sparse matrix to obtain product matrix data.
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