FERROELECTRIC FIELD-EFFECT MEMORY DEVICE
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United States of America Patent
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Jun 20, 2024
app pub date -
Dec 14, 2023
filing date -
Dec 14, 2023
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Abstract
The disclosed technology relates to a ferroelectric field-effect transistor (FeFET) memory structure. The FeFET memory structure can include a substrate, including an insulator layer; a gate metal layer on the insulator layer; at least one ferroelectric material layer on the gate metal layer; and a layer structure comprising at least one wide bandgap semiconductor layer on the ferroelectric material layer, wherein the layer structure can include: a first section having a first height, and at least one second section having a second height that is smaller than the first height. The FeFET memory structure can further include a drain metal structure which is arranged on the first section of the layer structure, and one or more source metal structures, wherein each source metal structure is arranged on a respective second section of the layer structure.
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