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Abstract

A successive approximation register analog to digital converter includes a capacitor array circuit, a quantizer circuit, a delay adjustment circuit, a control logic circuit, and a detector circuitry. The capacitor array circuit samples input signals to generate first signals and is sequentially switched according to a first digital code. The quantizer circuit quantizes the first signals according to a first control signal to generate second signals and receives the first control signal via a signal path. The delay adjustment circuit is coupled in parallel with the signal path and selectively adjusts a propagation delay of the first control signal. The control logic circuit generates the first digital code according to the second signals. The detector circuitry detects whether a quantization of the quantizer circuit is completed to generate the first control signal.

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First Claim