Vernier phase locked loop
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United States of America Patent
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Oct 1, 2024
Grant Date -
Jun 20, 2024
app pub date -
Dec 15, 2022
filing date -
Dec 15, 2022
priority date (Note) -
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Abstract
An apparatus that measures elapsed time in digital systems with multiple clocks includes a vernier reference (VREF) configured to generate a reference counter signal with a numeric output and two reference clock signals. The apparatus also includes a plurality of synchronizer VPLLs configured to receive the reference counter signal and the two reference clock signals and generate a plurality of synchronized counters, each synchronized counter being co-linear with the reference counter and operating in a respective target clock domain.
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