SYSTEM WITH A LOW-DRIFT ON-CHIP OSCILLATOR WITH LOWERED SENSITIVITY TO RANDOM TELEGRAPH NOISE
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United States of America Patent
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Issued Date -
Jun 20, 2024
app pub date -
Nov 7, 2023
filing date -
Nov 7, 2023
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Abstract
A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.
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