METHOD OF REDUCING METAL GATE RESISTANCE FOR NEXT GENERATION NMOS DEVICE APPLICATION

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United States of America Patent

APP PUB NO 20240204061A1
SERIAL NO

18067979

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Abstract

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Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CALIFORNIA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ailihumaer, Tuerxun Santa Clara, US 12 0
Chen, Shih Chung Cupertino, US 48 518
Devrajan, Janardhan Santa Clara, US 8 1
Gandikota, Srinivas Santa Clara, US 214 6856
Lei, Yu Belmont, US 136 1885
Lin, Yongjing San Jose, US 28 81
Liu, Zhihui Sunnyvale, US 35 95
Ma, Tengzhou San Jose, US 8 0
Sriram, Mandyam San Jose, US 77 7695
Xu, Yi San Jose, US 319 2238
Yang, Yixiong Fremont, US 90 569
Zheng, Yuanhua Burlingame, US 5 1

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