SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS
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United States of America Patent
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Issued Date -
Jun 20, 2024
app pub date -
Oct 12, 2023
filing date -
Oct 12, 2023
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Abstract
An apparatus that includes a plurality of first memory mats each including a plurality of normal column sections each storing user data, and a second memory mat including a plurality of first redundant column sections each substituting a defective one of column sections included in the plurality of first memory mats and a plurality of first BCC column sections each storing an error correction code.
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