PLL CIRCUIT AND TRANSMISSION SYSTEM
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United States of America Patent
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Jun 6, 2024
app pub date -
Feb 14, 2024
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Aug 25, 2021
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Abstract
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
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