PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS
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United States of America Patent
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Jun 6, 2024
app pub date -
Jan 24, 2024
filing date -
May 28, 2020
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Abstract
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
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