SEMICONDUCTOR CHIP
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United States of America Patent
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Issued Date -
May 23, 2024
app pub date -
Nov 17, 2023
filing date -
Nov 18, 2022
priority date (Note) -
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status (Latency Note)
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Abstract
A plurality of SRAM macros each including a memory cell array, an input/output circuit, a word line driver, and a control circuit are mounted on a semiconductor chip. Each of the SRAM macros includes a determination block disposed in the control circuit and configured to generate a mode signal for determining a read assist amount and a write assist amount based on a power supply voltage of the SRAM macro, and an assist circuit that performs a read assist operation and a write assist operation based on the mode signal generated by the determination block.
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