Multi-port, multi-protocol varied size RAM controller
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United States of America Patent
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May 28, 2024
Grant Date -
May 23, 2024
app pub date -
Nov 18, 2022
filing date -
Nov 18, 2022
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Abstract
A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.
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